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11/11/2014, Prof. Baker (U. Nevada, USA) Talk:Low-Power, High-Bandwidth, and Ultra-Small Memory Module Design

posted Nov 4, 2014, 7:29 AM by Amine M   [ updated Mar 22, 2015, 3:24 PM ]
Event Co-organized by IEEE-EMB/CAS Québec Chapter and IEEE-SSCS
Laval University, Adrien-Pouliot Build. Room PLT-1122 
Tuesday November 11th, 2014, from 10AM to 11AM


Short Biography






R. Jacob Baker is a Professor of Electrical and Computer Engineering at the University of Nevada, Las Vegas. His research interests lie in integrated electrical/biological circuits and systems, interfacing CMOS to Silicon Photonics, and the delivery of online engineering education. He has extensive industry experience and is the author of several circuit design books. Additional information can be found at http://CMOSedu.com.


Abstract

This work proposes a novel DRAM module and interconnect architectures in an attempt to improve computing energy use and performance. A low cost advanced packaging technology is used to propose an 8 die and 32-die memory module. The 32-die memory module measures less than 2 cm3. The size and packaging technique allow the memory module to consume less power than conventional module designs. A 4 Gb DRAM architecture utilizing 64 data pins is proposed. The DRAM architecture is inline with ITRS roadmaps and can consume 50% less power while increasing bandwidth by 100%. The large number of data pins are supported by a low power capacitive-coupled interconnect. The receivers developed for the capacitive interface were fabricated in 0.5 μm and 65 nm CMOS technologies. The 0.5 μm design operated at 200 Mbps, used a coupling capacitor of 100 fF, and consumed less than 3 pJ/bit of energy. The 65 nm design operated at 4 Gbps, used a coupling capacitor of 15 fF, and consumed less than 15 fJ/bit and order of magnitude smaller consumptions than previously reported receiver designs.


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