New Packaging Techniques for Hybrid Microsystems

Our research expertise targets new packaging technique ifor hybrid microelectronics / microfluidic microsystems. We targetting very thin LoC including microchannels and complementary-metal-oxide semiconductor (CMOS) chip. We use glass, PDMS, silicon, epoxies and other type materials. Our previous device has a thickness of 0.5 mm. The size of the device is 5 mm x  5 mm including 64 L-shaped electrodes. It was connected to a printed circuit board for cell manipulation using dielectrophoresis. The device also includes a new polydimethylsiloxane (PDMS)-based packaging technique to protect the integrated circuit (IC) from liquid leakage, in addition to a fast tubing process. The designed LoC requires only 2 picoliters as sample volume. Different packaging scenarios were tested using ultraviolet light and conventional epoxy, as well as PDMS and commercial connectors